Mixed analog and digital systems utilize analog-to-digital converters (ADCs) to convert the voltages of analog signals to corresponding digital values for use by digital components. Redundant signed bit (RSD) and other cyclic or pipelined ADCs often find particular benefit in certain types of systems, particularly where power and space are at a premium. These ADCs typically convert an analog signal to a corresponding digital value through a series of sample and amplify phases. During the initial phase, the voltage of the input analog signal is compared to two or more reference voltages and the results of these comparisons are provided as code bits for the initial stage. An analog component comprising a multiplying digital-to-analog converter (MDAC) is used to determine a residue voltage, and for a second phase the process of comparisons with the reference voltages is repeated with the residue voltage to generate code bits for a third phase. The process of calculating the residue voltage from the residue voltage of the previous stage and comparing the resulting residue voltage to generate code bits can be repeated for a number of phases until the appropriate resolution is reached. An alignment, synchronization, and correction process then is applied to the code values from each stage to generate a digital value representative of the analog signal.
In conventional ADCs each capacitor of the MDAC is reconnected to the amplifier of the MDAC for successive phases such that the same capacitor is connected in the same configuration within the MDAC for the same phase of a conversion cycle. Due to capacitor mismatches in this fixed capacitor configuration and the finite gain of the amplifier, a conventional ADC can experience large steps in the integral non-linearity (INL) at comparator trip points. This non-linearity can introduce significant spurious harmonics, thereby reducing the spurious free dynamic range (SFDR) of the ADC. One approach to improve the dynamic range of an ADC is to reduce capacitor mismatch by implementing larger capacitors that can be more precisely matched. However, larger capacitors require a greater area and consume more power and their use therefore is contrary to goals of reduced power consumption and size. An improved technique for reducing the effects of capacitor mismatch in ADCs without necessitating the use of larger capacitors therefore would be advantageous.